The invention relates to an arithmetic and logic computation device and a control method. This device and this method can be applied notably to all arithmetic processors or signal processors. It can be used to carry out double precision computations, especially double precision multiply (or multiplication) operations and multiply-accumulate (or multiplication-accumulation) operations.
Carrying out double precision or multi-precision computations implies working with operands that are greater than the data buses, for example working with 32-bit operands on 16-bit data buses.
To carry out multiplication-accumulation operations, a multiplier and an arithmetic and logic unit are used. The multiplier carries out the multiplication between two operands and places the product in a register. The arithmetic and logic unit adds the product to the result contained in an accumulation register.
To carry out double precision multiply operations, when the multiplier accepts operands having the width of the data bus at input, it is necessary to compute elementary products and add these products to obtain the result of the multiplication.
An elementary product is defined as a product computed with operands having the width of the data bus. In the case of a 16-bit data bus, for a double precision multiply operation on 32-bit operands, each formed by a word of 16 most significant bits and 16 least significant bits, four elementary products are computed: the product of the two least significant words and, the product of the two most significant words and the two "crossed" products of the least significant word of one operand crossed with the most significant word of the other operand. The elementary products are expressed on 2.times.16 bits.
One of the problems encountered is that of adding the different elementary products together to obtain the final result on 2.times.32 bits and, for a multiplication-accumulation operation, of adding these elementary products to an intermediate result. To add the 32-bit elementary products properly, they must be aligned at the right place in the window of the 64-bit result. For this purpose, if necessary, the intermediate result is shifted and the elementary product is added to it. The intermediate result should therefore be saved before the shifting so as not to lose bits in the result, which makes it necessary to manage different pointers in the memory. For example, if there is a 16-bit multiplier and a 32-bit adder and if it is desired to multiply two 32-bit numbers x1x0 and y1y0 (x1, y1 representing the most significant word and x0, y0 representing the least significant word) and accumulate this product in a 32-bit accumulator, A=A.sub.high +A.sub.low (A.sub.high representing the 16 most significant bits and A.sub.low representing the 16 least significant bits), the following different operations will be carried out:
x0*y0+A in A
A.sub.low in m0
x1*y0+A*2.sup.-16 in A
x0*y1+A in A
A.sub.low in m1
x1*y1+A*2-16 in A.
Since all these additions are done on the accumulator and since this accumulator is always shifted to the right, the carry and the sign bit propagate naturally in the accumulator.
To obtain multiplication-accumulation loops, it is necessary to carry out operations on the memory zones m0 and m1 and on the accumulator A, since the result is no longer aligned and since it is partly in m0 (16 least significant bits), partly in the accumulator (32 most significant bits) and partly in m1 (16 middle bits). This increases the number of instruction cycles necessary and may entail heavy penalties.
It is an object of the invention to facilitate the double precision and more generally the multi-precision operations, notably by avoiding memory operations. It is also an object of the invention to reduce the number of instruction cycles needed for such operations.
According to the invention, a shifter is placed on an input of the arithmetic and logic unit. To add a crossed product of the x0*y1 type, this product is applied to the arithmetic and logic unit, to the input with shifter. Thus, it is the product that is aligned with the accumulator and not the contrary.
As claimed, the invention relates to an arithmetic and logic computation device comprising an arithmetic and logic unit. According to the invention, a shifter is provided on at least one input of the arithmetic and logic unit.
Advantageously, the shifter is a barrel shifter. A shifter of this kind is very flexible in its use, enabling logic and arithmetic shifting operations.
The computation device according to the invention furthermore comprising at least two accumulators, one multiplier and one control unit, can be used to carry out instructions for the double accumulation of a product computed by a multiplier, with a first accumulation on a first accumulator with a rightward arithmetic shift of the product and a second accumulation on a second accumulator with a leftward shift of the product.
However, by carrying out two accumulations on two different accumulators, the natural propagation of the carry is lost in the multiplication-accumulation operations.
In the invention, there is provision for means to propagate the carry. Preferably, the arithmetic and logic computation unit having a first register to memorize the carry computed in the current operation and to give this carry in the next operation, the propagation means include a first circuit and a second register, the first circuit being controlled by a control signal delivered by the control unit to save the carry computed by the arithmetic and logic unit either in the first register or in the second register. The first circuit is advantageously a multiplexer/demultiplexer.
According to a second characteristic of the invention, the arithmetic and logic computation device comprises a second circuit controlled by the control unit for the application or non-application of the carry memorized in the first register, to the stage of computing the least significant bit in the multiplier. The second circuit is advantageously an AND gate receiving, at input, the output of the first register and a binary control signal delivered by the control unit.
The invention also relates to a method for the control of a computation device comprising a multiplier with an associated product register, an arithmetic and logic unit with two inputs and at least one shifter at one input of the arithmetic and logic unit. According to the invention, the control method consists, for an instruction comprising an accumulation in an accumulator and a multiplication, in:
applying the contents of the product register to an input of the arithmetic and logic unit and sending a computation signal of the accumulation to the arithmetic and logic unit; PA1 sending a signal for the computation of a new product to the multiplier. PA1 the protection of the first carry register, to keep the carry computed in the previous instruction; PA1 the application of the contents of the product register to the input with shifter; PA1 a first accumulation of the contents of the product register arithmetically shifted by n bits towards the left by the shifter with the contents of the first accumulator, with memorization of the carry in a second register; PA1 a second accumulation of the contents of the product register shifted arithmetically by n bits to the right by the shifter with the contents of the second accumulator and the carry bit memorized in the second register.
The invention also relates to a control method for the computation of a double accumulation of a product comprising a word of n most significant bits and a word of n least significant bits, the arithmetic and logic unit comprising at least one first accumulator and one second accumulator, a first register to memorize the carry computed by the arithmetic and logic unit for the current instruction and a second register. According to the invention, the control method consists upon the reception of an instruction comprising a double accumulation of the product, in:
To compute a double precision multiplication of two operands, each operand of the product to be computed comprising a word of n most significant bits and a word of n least significant bits, the control method according to the invention further activates, in parallel with the second accumulation, a multiplication operation by the application or non-application of the carry contained in the first register to the computation stage of the least significant bit of the product in the multiplier.